Silicon Labs /EFR32MG21A020F768IM32 /USART0_S /TIMECMP0

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Interpret as TIMECMP0

31282724232019161512118743000000000000000000000000000000000000000000TCMPVAL0 (DISABLE)TSTART0 (TCMP0)TSTOP0 (DISABLE)RESTARTEN

RESTARTEN=DISABLE, TSTOP=TCMP0, TSTART=DISABLE

Description

No Description

Fields

TCMPVAL

Timer comparator 0.

TSTART

Timer start source

0 (DISABLE): Comparator 0 is disabled

1 (TXEOF): Comparator 0 and timer are started at TX end of frame

2 (TXC): Comparator 0 and timer are started at TX Complete

3 (RXACT): Comparator 0 and timer are started at RX going going Active (default: low)

4 (RXEOF): Comparator 0 and timer are started at RX end of frame

TSTOP

Source used to disable comparator 0

0 (TCMP0): Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event

1 (TXST): Comparator 0 is disabled at TX start TX Engine

2 (RXACT): Comparator 0 is disabled on RX going going Active (default: low)

3 (RXACTN): Comparator 0 is disabled on RX going Inactive

RESTARTEN

Restart Timer on TCMP0

0 (DISABLE): Disable the timer restarting on TCMP0

1 (ENABLE): Enable the timer restarting on TCMP0

Links

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